The desire for higher packing densities, faster circuit speed, and lower power dissipation has driven the scaling of semiconductor devices to smaller dimensions. Feature sizes for channel length, for example, have approached 0.1 μm (100 nm) for devices such as metal-oxide-semiconductor field effect transistors (MOSFETs). As the channel length of these devices decrease below 100 nm, however, problems arise.
One problem is that the gate oxide thickness must be reduced in proportion to the channel length to control short-channel effects and maintain a good subthreshold turn-off slope. As the thickness of the gate oxide decreases, quantum mechanical tunneling becomes a factor which leads to increased gate leakage. One solution to this problem is to form a corner dominated semiconductor device, which for a given oxide thickness, results in a steep subthreshold slope. Such a device should also be engineered to ensure that the effective area of current flow is not diminished.
A conventional corner dominated semiconductor device using triangular wire channels increases the number of corners and the area of current flow by providing a two-fold increase in the number of wire channels compared to a pillar- or rectangular-shaped wire channel. FIGS. 1A–1C show a conventional method of forming a triangular channel array. As shown in FIG. 1A, the conventional triangular channel array is made by forming a lithographic line pattern 30 on a silicon layer 20. In FIG. 1B, a first isotropic etch removes a portion of silicon layer 20 to form a plurality of structures 23 having sloped sidewalls. A selective oxidation forms an SiO2 layer 40 on the sloped sidewalls of structures 23. Referring to FIG. 1C, lithographic line pattern 30 is removed and a second isotropic etch is performed. The second isotropic etch removes another portion of structures 23 to form additional sloped sidewalls that, together with the sloped sidewalls formed from the first isotropic etch, form a conventional parallel triangular wire array 25.
Conventional methods for forming corner dominated semiconductor devices, however, are limited to forming only two triangles for each lithographic line pattern 30. Further, the pitch of the resultant wire channel array is limited to two times the width of the lithographic line pattern, also called the “critical dimension.”
Thus, there is a need to overcome these and other problems of the prior art and to provide a pitch multiplication process that increases the number of corners and maximizes the current flow area.